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MIT provost Chandrakasan wins test of time award
The ‘Test of Time’ award, established in 2024, recognizes outstanding research published in the IEEE Journal of Solid-State Circuits that has had significant and measurable impact on the field.
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Pranavi Sharma - Thu, 02, Apr 2026
- 01:52 EDT
- 39
Anantha P. Chandrakasan / MIT
Anantha P. Chandrakasan, an Indian American engineer born in Chennai, has been named a recipient of the 2025 ‘Test of Time’ award for his co-authored paper ‘Low-Power CMOS Digital Design,’ recognizing its long-term impact on the field of integrated circuits.
The award honors a paper published in the April 1992 issue of the IEEE Journal of Solid-State Circuits that has demonstrated sustained influence over at least a decade. Chandrakasan shares the recognition with co-authors Sam Sheng and Robert W. Brodersen, both affiliated with the University of California, Berkeley at the time of publication.
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Chandrakasan currently serves as provost and the Vannevar Bush Professor of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology in Cambridge, Massachusetts. He also holds multiple leadership roles at the institute, including chair of the MIT Climate and Sustainability Consortium and the MIT AI Hardware Program. He is co-chair of several initiatives, including the MIT–IBM Watson AI Lab, the MIT and Accenture Convergence Initiative for Industry and Technology, and the Tata-MIT Alliance.
In addition, he leads the MIT Health and Life Sciences Collaborative and the MIT Generative AI Impact Consortium, and co-chairs the MIT Human Insight Collaborative and the MIT-GE Vernova Energy and Climate Alliance.
Born in Chennai, Chandrakasan moved to the United States during high school. His mother, a biochemist, was a Fulbright Scholar. He earned his bachelor’s degree in 1989, master’s degree in 1990, and doctorate in electrical engineering and computer sciences in 1994 from the University of California, Berkeley.
The ‘Test of Time’ award, established in 2024, recognizes outstanding research published in the IEEE Journal of Solid-State Circuits that has had significant and measurable impact on the field. Selection criteria include technical excellence, clarity, originality, and evidence of long-term influence, such as citations, use in patents, and application in products.
The award is presented every two years, provided a suitable recipient is identified. Each co-author receives a certificate and a $250 cash prize, with total prize distribution capped at $3,750.
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